POWER

See also on Wikipedia: IBM POWER and PowerPC

POWER is an acronym which stands for for Performance Optimization With Enhanced RISC. It was used as the name of a 32-bit processor architecture jointly developed by IBM, Apple and Motorola in 1991.

It referred to a RISC processor which was "superscalar", that is, was able to submit multiple instructions to multiple execution pipelines in a single processor cycle.

The successor architecture, PowerPC, was based POWER, but added the ability to support multiple processors, as well as expanding to 64-bit addressing and operations.

And its successor architechture, Amazon, expanded the PowerPC "definition to support single-level store, decimal arithmetic, high-speed data movement, improved branching, fast call/return, and other functions needed in a commercial server" as well as "capabilities...for a multi-user, multi-application system."

All processors listed below are 64-bit.

PowerPC AS Processors

PowerPC AS was the term given for the processor architecture for the first two processors, Muskie and Cobra. "Most people thought AS was for Advanced Series, but many of us preferred to think it was for Amazon Series".

Muskie

• 1995 - 154 MHz
• 1995 - 182 MHz
• Architecture: 64-bit Amazon
• 5 instruction execution pipelines, but it could dispatch only four instructions in a given cycle (it was a four-way superscalar design)
• 25 million transistors
• instruction cache had 8 K, organized 32 bytes wide
• L1 cache: 8 K (on-chip) instruction cache and an 256 K (on-chip) data cache
• L2 cache: ? MB (off-chip)
• Supported up to four-way symmetric multiprocessing (SMP)

Cobra

• 1995 - 50 MHz and 77 MHz
• Architecture: 64-bit Amazon
• 5 instruction execution pipelines, but it could dispatch only three instructions in a given cycle (it was a three-way superscalar design)
• 4.7 million transistors
• L1 cache: 4 K (on-chip) instruction cache and an 8 K (on-chip) data cache
• L2 cache: 1 MB (off-chip)

Apache (aka RS64)

• 1997 - 125 MHz, and other slower MHz
• 64-bit
• Architecture: 64-bit Amazon, 64-bit PowerPC, and 32-bit PowerPC
• Based on Cobra
• Supported up to twelve-way symmetric multiprocessing (SMP)
• "As a result of this full PowerPC implementation, Apache was the first Rochester-developed microprocessor ever to be used in another IBM system. Models of both the RS/6000 and AS/400e used Apache. This was the beginning of the effort described earlier in this chapter to merge the hardware of the AS/400 and RS/6000 product lines into one common platform. When used in the RS/6000, Apache was called the RS64 microprocessor."

Star Series Processors

• Architecture: 64-bit Amazon, 64-bit PowerPC, and 32-bit PowerPC
  • "Bit settings in processor-control registers on the chip determine which architecture mode is being used. These settings can be changed as the workload in the processor switches from one process to another. Thus, a single processor at one moment can operate as an Amazon processor and at the next moment as a pure PowerPC processor. This ability to switch from one architectural mode to another in the same processor would later let the AS/400 incorporate an AIX runtime environment."

Northstar (aka RS64-II)

• 1998 - 262 MHz
• 12.5 million transistors
• Supported up to twelve-way symmetric multiprocessing (SMP)
• L1 cache: 64 K (on-chip) instruction cache and an 64 K (on-chip) data cache
• L2 cache: 32 MB (off-chip)

Pulsar (aka RS64-III)

• 1999 on RS/6000, 2000 on AS/400 - 450 MHz
• 34 million transistors
• Supported up to twenty-four-way symmetric multiprocessing (SMP)
• L1 cache: 128 K (on-chip) instruction cache and an 128 K (on-chip) data cache
• L2 cache: 8 MB (off-chip)
• used on-chip copper wiring

I-Star

• 2000 on AS/400 - 540 MHz
• 34 million transistors
• the first processor to use both IBM’s copper and SOI technologies
• L1 cache: 128 K (on-chip) instruction cache and an 128 K (on-chip) data cache
• L2 cache: 8 MB (off-chip)

iSeries

• October 2000
• Used Pulsar or I-Star processors initially, later S-Star
  • "The copper-colored stripe on the front panel of each iSeries model proudly identified the technology within."

S-Star (aka RS64-IV)

• 44 million transistors
• L1 cache: 128 K (on-chip) instruction cache and an 128 K (on-chip) data cache
• L2 cache: 16 MB (off-chip)