Difference between revisions of "POWER"
From MidrangeWiki
MrDolomite (talk | contribs) (new page explaining processor architectures) |
MrDolomite (talk | contribs) m (adding 3x specific processors) |
||
| Line 6: | Line 6: | ||
The successor architecture, '''PowerPC''', was based {{AN}}, but added the ability to support multiple processors, as well as expanding to 64-bit addressing and operations.<ref name="Soltis" /> | The successor architecture, '''PowerPC''', was based {{AN}}, but added the ability to support multiple processors, as well as expanding to 64-bit addressing and operations.<ref name="Soltis" /> | ||
| − | And its successor architechture, '''Amazon''', expanded the PowerPC "definition to support single-level store, decimal arithmetic, high-speed data movement, improved branching, fast call/return, and other functions needed in a commercial server"<ref name="Soltis" /> as well as "capabilities...for a multi-user, multi-application system."<ref name="Soltis" /> | + | And its successor architechture, '''Amazon''', expanded the PowerPC "definition to support single-level store, decimal arithmetic, high-speed data movement, improved branching, fast call/return, and other functions needed in a commercial server"<ref name="Soltis" /> as well as "capabilities...for a multi-user, multi-application system."<ref name="Soltis" /> |
| + | |||
| + | '''PowerPC AS''' was the term given for the processor architecture for the first two processors, [[Muskie]] and [[Cobra]]. "Most people thought AS was for Advanced Series, but many of us preferred to think it was for Amazon Series".<ref name="Soltis" /> | ||
| + | |||
| + | ;Muskie | ||
| + | *1995 - 154 MHz | ||
| + | *1995 - 182 MHz | ||
| + | *64-bit | ||
| + | *Architecture: 64-bit Amazon | ||
| + | *5 instruction execution pipelines, but it could dispatch only four instructions in a given cycle (it was a four-way superscalar design) | ||
| + | *25 million transistors | ||
| + | *instruction cache had 8 K, organized 32 bytes wide | ||
| + | *L1 cache: 8 K (on-chip) instruction cache and an 256 K (on-chip) data cache | ||
| + | *L2 cache: ? MB (off-chip) | ||
| + | *Supported up to four-way symmetric multiprocessing (SMP) | ||
| + | |||
| + | ;Cobra | ||
| + | *1995 - 50 MHz and 77 MHz | ||
| + | *64-bit | ||
| + | *Architecture: 64-bit Amazon | ||
| + | *5 instruction execution pipelines, but it could dispatch only three instructions in a given cycle (it was a three-way superscalar design) | ||
| + | *4.7 million transistors | ||
| + | *L1 cache: 4 K (on-chip) instruction cache and an 8 K (on-chip) data cache | ||
| + | *L2 cache: 1 MB (off-chip) | ||
| + | |||
| + | ;Apache | ||
| + | *1997 - 125 MHz, and other slower MHz | ||
| + | *64-bit | ||
| + | *Architecture: 64-bit Amazon, 64-bit PowerPC, and 32-bit PowerPC | ||
| + | *Based on Cobra | ||
| + | *Supported up to twelve-way symmetric multiprocessing (SMP) | ||
| + | *"As a result of this full PowerPC implementation, Apache was the first Rochester-developed microprocessor ever to be used in another IBM system. Models of both the RS/6000 and AS/400e used Apache. This was the beginning of the effort described earlier in this chapter to merge the hardware of the AS/400 and RS/6000 product lines into one common platform. When used in the RS/6000, Apache was called the RS64 microprocessor."<ref name="Soltis" /> | ||
==References== | ==References== | ||
Revision as of 20:20, 28 April 2008
POWER is an acronym which stands for for Performance Optimization With Enhanced RISC.[1] It was used as the name of a 32-bit processor architecture jointly developed by IBM, Apple and Motorola in 1991.
It referred to a RISC processor which was "superscalar", that is, was able to submit multiple instructions to multiple execution pipelines in a single processor cycle.
The successor architecture, PowerPC, was based POWER, but added the ability to support multiple processors, as well as expanding to 64-bit addressing and operations.[1]
And its successor architechture, Amazon, expanded the PowerPC "definition to support single-level store, decimal arithmetic, high-speed data movement, improved branching, fast call/return, and other functions needed in a commercial server"[1] as well as "capabilities...for a multi-user, multi-application system."[1]
PowerPC AS was the term given for the processor architecture for the first two processors, Muskie and Cobra. "Most people thought AS was for Advanced Series, but many of us preferred to think it was for Amazon Series".[1]
- Muskie
- 1995 - 154 MHz
- 1995 - 182 MHz
- 64-bit
- Architecture: 64-bit Amazon
- 5 instruction execution pipelines, but it could dispatch only four instructions in a given cycle (it was a four-way superscalar design)
- 25 million transistors
- instruction cache had 8 K, organized 32 bytes wide
- L1 cache: 8 K (on-chip) instruction cache and an 256 K (on-chip) data cache
- L2 cache: ? MB (off-chip)
- Supported up to four-way symmetric multiprocessing (SMP)
- Cobra
- 1995 - 50 MHz and 77 MHz
- 64-bit
- Architecture: 64-bit Amazon
- 5 instruction execution pipelines, but it could dispatch only three instructions in a given cycle (it was a three-way superscalar design)
- 4.7 million transistors
- L1 cache: 4 K (on-chip) instruction cache and an 8 K (on-chip) data cache
- L2 cache: 1 MB (off-chip)
- Apache
- 1997 - 125 MHz, and other slower MHz
- 64-bit
- Architecture: 64-bit Amazon, 64-bit PowerPC, and 32-bit PowerPC
- Based on Cobra
- Supported up to twelve-way symmetric multiprocessing (SMP)
- "As a result of this full PowerPC implementation, Apache was the first Rochester-developed microprocessor ever to be used in another IBM system. Models of both the RS/6000 and AS/400e used Apache. This was the beginning of the effort described earlier in this chapter to merge the hardware of the AS/400 and RS/6000 product lines into one common platform. When used in the RS/6000, Apache was called the RS64 microprocessor."[1]
